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Furukawa Review No.31

Development of Wafer-Level Chip Size Package (WL-CSP)

Toshiaki Asada, Toshiaki Amano, Kazuhito Hikasa, Ken'ichi Sugahara,Hirofumi Oshima and Yoshimi Ono

Abstract

Recently electronic equipment have remarkably improved becoming more compact and lighter and having upgraded function, requiring semiconductor packages mounted thereon to be more compact, thin-bodied and lightweight as well as to enable high-density mounting on substrates. Thus a new semiconductor package called wafer-level chip size package (hereafter called WL-CSP) technology is drawing attention. In response to such situations, the authors have developed a new WL-CSP, in which a tape substrate is bonded with wafers in a continuous roll-to-roll manufacturing process enabling cost reduction and quick delivery, and a resin post structure is adopted for the terminal pads to ensure high reliability. This paper reports on the structure, manufacturing process and results of prototype manufacturing of Furukawa Electric's original WL-CSP, together with its features and reliability test results.

Open PDF file.Full Text PDF(2,279KB)

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